1. Field of the Invention
The present invention relates to a chipset, and more particularly, to a method for supporting a monitor to display with a chipset and related computer system.
2. Description of the Prior Art
Please refer to FIG. 1, which is a functional block diagram of a computer system 40 having a K8 CPU 42 produced by AMD according to the prior art. The computer system 40 further includes a chipset composed of a north bridge 44 and a south bridge 46, a system memory 18 couples to the CPU 42 directly, a monitor 22 coupled to the north bridge 44 for displaying graphics data, and some peripheral devices, such as a keyboard 24 and a hard disk 26, coupled to the south bridge 46.
When the CPU 42 processes high speed data logic operations, the CPU 42 is operated in high operating state, such as a power saving state C0. However, when the CPU 42 doesn't process high speed data logic operations, the CPU 42 is operated in power saving states, such C1, C2 or C3, to reduce power consumption.
When operating in the power saving state C0, the CPU 42 is at full speed and capable of receiving and executing instructions.
When operating in the power saving state C1, the CPU 42 stops receiving instructions to save power consumption.
When operating in the power saving state C2, the CPU 42 further stops outputting clocks.
When operating in the power saving state C3, the CPU 42 is unable to support a snoop operation.
When the CPU 42 doesn't operate at full speed, the CPU 42 is switched from the power saving state CO to the power saving state C3. When switching CPU Power states, the operating system sends an STPCLK signal through the south bridge 46 to the CPU 42. After the CPU 42 is ready to be switched, the south bridge 46 sends an asserted LDTSTOP# (‘#’ means low voltage enabled) signal to the north bridge 44 and CPU 42. Then the CPU 42 enters the power saving state C3, and the north bridge 44 disconnects to the CPU 42. As a result, the snoop operation cannot be performed between the north bridge 44 and the CPU 42.
When the south bridge 46 receives a bus master signal or an interrupt, power states of the CPU 42 has to be switched from a deeper power saving state (for example C3) to a shallower power saving state (for example C2 to C0). Thus the south bridge 46 sends de-asserted LDTSTOP# signal to the north bridge 44 and CPU 42 for entering the CPU 42 into a shallower power saving state and reconnecting the north bridge 44 and the CPU 42. Therefore, the bus master signal and the interrupt can function normally.
Since the monitor 22 has to display graphics data continuously and the data must be access form the system memory 18 through the CPU 42. When the south bridge 46 sends the asserted LDTSTOP# signal to disconnect the north bridge 44 and the CPU 42, whether the graphics data stored in a buffer of the north bridge 44 is sufficient is not controllable. Therefore, if the graphics data stored in the buffer is not sufficient, the CPU 42 has to be switched to operate in a shallower power saving state, and then more graphics data can be acquired from the system memory 18. If the time it takes for the CPU 42 to be switched to operate from the power saving state C3 to the power state C0 is long, and the CPU 42 cannot acquire enough graphics data in time, the monitor 22 encounters a display interruption problem.
Taking the example of switching power state from a deeper power saving state to the power saving state C0, when the north bridge 44 determines that the graphics data stored in the buffer is not sufficient for the monitor 22 to display, the north bridge 44 sends an AGP BUSY signal to the south bridge 46. Then, the south bridge 46 sends the de-asserted LDTSTOP# to the north bridge 44 and the CPU 42 for switching the CPU 42 to a shallower power saving state and reconnecting the north bridge 44 and the CPU 42, and then performing graphics data access from the system memory 18.
However the time consumption of the above mention steps, from sending signals to completing confirmation, is longer than that the time for the buffer in the north bridge 44 to output graphics data. This problem is more serious especially in a graphic integrated chipset due to the complicated inner circuit without having enough space for data storage.